32016

NS 32000 registers

31 . . . 23 . . . 15 . . . 07 . . . 00 (bit position) General registers R0 Register 0 R1 Register 1 R2 Register 2 R3 Register 3 R4 Register 4 R5 Register 5 R6 Register 6 R7 Register 7 Index registers 0000 0000 SP1                           Stack Pointer (user) 0000 0000 SP0                           Stack Pointer (interrupt) 0000 0000 SB                           Static Base 0000 0000 FP                           Frame Pointer 0000 0000 INTBASE                        Interupt Base Program counter 0000 0000 PC                           Program Counter   MOD Module descriptor Program Status Register   15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position)   – – – – I P S U N Z F – – L T C PSR

The 320xx or NS32000 was a series of microprocessors from National Semiconductor. They were likely the first 32-bit general-purpose microprocessors on the market, but due to a number of factors they never became commercially successful. The 320xx series was also used as the basis of the Swordfish microcontroller. It was replaced by the CompactRISC architecture in mid-1990s.

The processors had 8 general-purpose 32-bit registers, plus a series of special-purpose registers:

(Additional system registers not listed).

The instruction set was very much in the CISC model, with 2-operand instructions, memory-to-memory operations, flexible addressing modes, and variable-length byte-aligned instruction encoding. Addressing modes could involve up to two displacements and two memory indirections per operand as well as scaled indexing, making the longest conceivable instruction 23 bytes. The actual number of instructions was much lower than that of contemporary RISC processors.

Unlike some other processors, autoincrement of the base register was not provided; the only exception was a "top of stack" addressing mode that would pop sources and push destinations. Uniquely, the size of the displacement was encoded in its most significant bits: 0, 10 and 11 preceded 7-, 14- and 30-bit signed displacements. (Although the processors were otherwise consistently little-endian, displacements in the instruction stream were stored in big-endian order).

General-purpose operands were specified using a 5-bit field. To this could be added an index byte (specifying the index register and 5-bit base address), and up to 2 variable-length displacements per operand.

The original 32016 had a 16-bit external databus, a 24-bit external address bus, and a full 32-bit instruction set. It also included a coprocessor interface, allowing coprocessors such as FPUs and MMUs to be attached as peers to the main processor. The MMU was based on demand paging Virtual Memory, which was the most unusual feature compared to the segmented memory approach used by competition, and has become the standard for how microprocessors are designed today. The architecture supported an instruction restart mechanism on a page fault, which was much cleaner than the Motorola approach to dump the internal status on a page fault, which had to be read back, before the instruction was continued. Again, the Series 32000 approach has become the standard behavior.

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