Puma (microarchitecture)
| Produced | From mid-2014 to present |
|---|---|
| Common manufacturer(s) | |
| Max. CPU clock rate | 1.35 GHz to 2.5 GHz |
| Min. feature size | 28 nm |
| Instruction set | AMD64 (x86-64) |
| Cores | 2–4 |
| L1 cache | 64 KB per core |
| L2 cache | 1 MB to 2 MB shared |
| Socket(s) |
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| Predecessor | Jaguar - Family 16h |
| GPU | Radeon Rx: 128 cores, 300–800 Mhz |
| Core name(s) |
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| Brand name(s) |
The Puma Family 16h is a low-power microarchitecture by AMD for its APUs. It succeeds the Jaguar as a second-generation version, targets the same market, and belongs to the same AMD architecture Family 16h. The Beema line of processors are aimed at low-power notebooks, and Mullins are targeting the tablet sector.
The Puma cores use the same microarchitecture as Jaguar, and inherits the design:
Like Jaguar, the Puma core has support for the following instruction sets and instructions: MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, BMI1, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM (POPCNT/LZCNT), and AMD-V.
AMD released a revision of Puma core, Puma+, as a part of the Carrizo-L platform in 2015. The differences in the CPU microarchitecture are unclear. Puma+ featured 2 or 4 cores up to 2.5GHz and required the newer FP4 socket.
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